In semiconductor fabrication integrated circuits and semiconducting devices are formed by sequentially forming features in sequential layers of material in a bottom-up manufacturing method. The manufacturing process utilizes a wide variety of deposition techniques to form the various layered features including various etching techniques such as anisotropic plasma etching to form device feature openings followed by deposition techniques to fill the device features. In order to form reliable devices, close tolerances are required in forming features including photolithographic patterning methods which rely heavily on layer planarization techniques to maintain a proper depth of focus.
Planarization is increasingly important in semiconductor manufacturing techniques. As device sizes decrease, the importance of achieving high resolution features through photolithographic processes correspondingly increases thereby placing more severe constraints on the degree of planarity required of a semiconductor wafer processing surface. Excessive degrees of surface nonplanarity will undesirably affect the quality of several semiconductor manufacturing process including, for example, in a photolithographic process, the positioning the image plane of the process surface within an increasingly limited depth of focus window to achieve high resolution semiconductor feature patterns.
One planarization process is chemical mechanical polishing (CMP). CMP is increasingly being used as a planarizing process for semiconductor device layers, especially for applications with smaller semiconductor fabrication processes, for example, below about 0.25 micron. CMP planarization is typically used several different times in the manufacture of a multi-layer semiconductor device, including preparing a layered device structure in a multi-layer device for subsequent processing. For example, CMP is used to remove excess metal after filling conductive metal interconnects such as vias and trench lines with metal, for example copper, to electrically interconnect the several layers and areas that make up a multilayer semiconductor device.
In the formation of conductive interconnections, copper is increasingly used for forming metal interconnects such as vias and trench lines since copper has low resistivity. The undesirable contribution to electrical parasitic effects by metal interconnect residual resistivity has become increasingly important as device sizes have decreased.
In a typical process for forming conductive interconnections in a multi-layer semiconductor device, a damascene process is used to form vias and trench lines for interconnecting different layers and areas of the multilayer device. Vias (e.g., V1, V2 etc. lines) are generally used for vertically electrically interconnecting semiconductor device layers and trench lines (e.g., M1, M2, etc. lines) are used for electrically interconnecting semiconductor device areas within a layer. Vias and trench lines are typically formed as part of a damascene process. Although there are several different methods for forming damascene structures, one typical method generally involves patterning and etching a semiconductor feature, for example a via opening within an insulating dielectric layer to make contact with a conductive area within an underlying layer of the multilayer device. The via opening (plug) may then be filled with, for example copper, to form a via (plug) followed by a CMP step to remove excess metal deposited on the insulating dielectric layer surface and to planarized the surface for a subsequent processing step. A second insulating dielectric layer is then deposited followed by patterning and etching the second insulating dielectric layer to form a trench opening situated over the via. The trench opening is then filled with a metal, for example, copper, to form trench lines which electrically communicate with other layers through conductive contact with vias and also electrically communicate with other areas within the layer by trench line metal interconnects. A second CMP step is then carried out similar to the first CMP step to remove excess metal and to planarize the process wafer surface in preparation for further processing.
CMP generally includes placing a process surface of the wafer in contact against a flat polishing surface, imparting a downforce to the wafer backside and moving the wafer and the polishing surface relative to one another. The polishing action is typically aided by a slurry which includes for example, small abrasive particles such as silica (SiO2) or alumina (Al2O3) that abrasively act to remove a portion of the process surface. Additionally, the slurry may include chemicals (e.g.,complexing agents and film forming agents) that react with the process surface to assist in removing a portion of the surface material, the slurry typically being separately introduced between the wafer surface and the polishing pad. During the polishing or planarization process, the wafer is typically pressed against a rotating polishing pad. In addition, the wafer may rotate and oscillate over the surface of the polishing pad to improve polishing effectiveness.
Typically CMP polishing slurries contain an abrasive material, such as silica or alumina, suspended in an aqueous medium. There are various mechanisms disclosed in the prior art by which metal surfaces can be polished with slurries. In one method, the formation of a thin oxide layer takes place in-situ by reaction between the metal surface and an oxidizing agent which simultaneously forms an oxide layer while an abrasive is removing the oxide layer. The thin abradable oxide layer including the underlying metal layer is thereby selectively removed in a controlled manner by mechanical abrasive action. The rate of material removal can be varied by adjusting the rate of oxide formation and material removal.
Several defects can be associated with CMP polishing. For example,in CMP polishing, metals, for example, copper in a dense array of metal interconnects is removed or eroded at a faster rate than the surrounding field of insulating dielectric. This causes a topography difference between insulating dielectric and the dense copper array, typically referred to as erosion. More highly abrasive materials included in a polishing slurry tend to exacerbate the problem. Another problem, is related to the chemical etching rate of the etchants included in a polishing slurry. A strong acid, for example leads to a higher chemical etching rates which may result in a dimensional difference over a polishing area, referred to as dishing, caused by differences in polishing rates over the polishing area. Another defect related to relatively highly abrasive materials is the phenomenon of peeling of dielectric layers when subjected to polishing induced stresses. The problem is exacerbated where low-k (dielectric constant) layers with copper metal interconnects are present. The generally more porous nature of the low-k layers presents adhesion problems with both copper interconnects and other low-k layers.
In a typical copper CMP process, in order to avoid plastic deformation induced defects (e.g., scratches and divots) into the copper metal surface caused by abrasive slurry particles, and to aid in global planarization (extending over the process wafer surface) by equalizing rates of material removal across the process wafer surface, a slurry including abrasive particles and a copper oxide forming chemical are used to achieve both copper oxide formation over the copper surfaces and a suitably selective planarization (surface material removal) rate over the entire process wafer surface.
For example, a typical copper CMP polishing slurry includes silica (SiO2) or alumina (Al2O3) abrasive particles, hydrogen peroxide (H2O2) and various acids or bases to adjust the pH of the slurry. The oxidizing agent, for example, hydrogen peroxide (H2O2), is used to oxidize the copper surface to form a thin layer of copper oxide which is simultaneously removed by the abrasive polishing process of the abrasive particles thereby creating a fresh copper surface for continued surface reaction between the hydrogen peroxide (H2O2) and the copper surface. The copper oxide is formed on the copper surface by an in-situ chemical reaction induced over the copper surface. The in-situ generated copper oxide typically includes an hydroxide of copper (e.g., Cu(OH)x) generally referred to herein as copper oxide typically coexisting with more familiar forms of copper oxide (e.g., CuO, Cu2O) formed by other ex-situ oxidation processes.
In another method of polishing copper surfaces, a complexing agent forms a complex by chelating a copper ion which is then removed by a lower hardness abrasive. The advantage of using a lower hardness abrasive is that defects such as dishing, erosion, divot formation, and peeling are minimized. For example, colloidal particles including silica (SiO2) and alumina (Al2O3) produced by sol-gel process to produce dispersed particles are typically less abrasive than the same material produced by a high temperature fuming process where larger agglomerates of the particles with sharper particle edges and denser material are produced.
Using either method of the prior art to polish copper containing surfaces has associated problems. For example, if an oxidizer is used to form an in-situ copper oxide film over the target polishing surface, a more highly abrasive material is required to remove the copper oxide layer leading to a higher rate of defect formation such as erosion, divot formation, and peeling. On the other hand, if a complexing agent is used for chelating a surface copper ion to form a complex for subsequent removal with a less abrasive material, the effectiveness of the process is inhibited if the more polishing resistant copper oxide is present on the surface. Copper oxides (e.g., CuO, Cu2O) are typically formed on copper surfaces by ex-situ oxidation processes including exposure to oxygen containing ambient. The ex-situ formed copper oxides (e.g., CuO, Cu2O) are more dense and more resistant to material removal compared to copper or in-situ formed copper oxide (hydroxide) e.g., Cu(OH)x. As a result, non-uniform copper oxide films present on the target polishing surface propagate non-uniformities in subsequent polishing processes. Non-uniformities in the polished surface, in turn, lead to variations in metal interconnect resistivities including residual copper left on the polishing surface.
For example, FIGS. 1A–1C are conceptual side view representations of a portion of a semiconductor wafer surface showing copper oxide formation and removal according to the prior art. In FIG. 1A is shown a layer of copper 14 overlying insulating dielectric layer 12, copper layer 14 showing an ideal representation of a newly formed copper surface 14A.
FIG. 1B shows the formation of copper oxide layer 16 over the copper surface 14A during a standard CMP process whereby an oxidizing chemical such as hydrogen peroxide oxidizes the copper surface to form an in-situ generated passivation film of copper oxide (e.g., Cu(OH)x).
FIG. 1C shows the undesirable consequence of the method according to the prior art where a low spot including the copper oxide film 16 is removed at a relatively slow rate while removing the copper oxide film 16 at a high spot e.g., 18, and leaving a portion of the copper oxide 16 film at a low spot, e.g., 20.
FIG. 1D shows a dense copper oxide (e.g., CuO, CuO2) film 22 formed on most copper surfaces by ambient oxidation processes (aging) of the copper surface. This copper oxide film typically includes the general formula CuO, Cu2O, being more dense compared to the in-situ generated copper oxide film (e.g., Cu(OH)x) produced during the slurry polishing process. As a result, the problem of uniformly removing an in-situ generated copper oxide film (e.g. Cu(OH)x) is exacerbated by the presence of the denser copper oxide film formed by ex-situ oxidation processes. The rate of surface material removal using an abrasive slurry of the prior art including an oxidizing chemical, for example, hydrogen peroxide, is much slower over a copper oxide surface compared to a copper surface.
Therefore, there is a need in the semiconductor art to develop a CMP method for planarizing dielectric layers including copper semiconductor features such that the CMP process results in a more uniform material removal rate with a lower level polishing induced defects.
It is therefore an object of the invention to provide a CMP method for planarizing dielectric layers including copper semiconductor features such that the CMP process results in a more uniform material removal rate with a lower level of polishing induced defects while overcoming other shortcomings and deficiencies in the prior art.